1. Field of the Invention
The present invention generally relates to Integrated Circuit (IC) manufacture and more particularly to reducing costs in semiconductor chip manufacture of integrated circuits with short channel Field Effect Transistors (FETs).
2. Background Description
Semiconductor technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). Shrinking/reducing device or field effect transistor (FET) feature sizes and, correspondingly, device minimum dimensions including horizontal dimensions (e.g., minimum channel length) and vertical dimensions (e.g., channel layer depth, gate dielectric thickness, junction depths and etc.) shrinks device size for increased device density and device performance, as well as reduces device operating conditions, i.e., chip and correspondingly, device supply voltages and voltage swings.
Generally, all other factors being constant, the active power consumed by a given unit increases linearly with switching frequency, i.e., performance. Thus, notwithstanding the decrease of chip supply voltage, chip power consumption has increased as well. Both at the chip and system levels, cooling and packaging costs have escalated as a natural result of this increase in chip power. Especially for low end systems (e.g., handhelds, portable and mobile systems), where battery life is crucial, reducing net power consumption is important. However, such a power reduction must come without degrading chip/circuit performance below acceptable levels.
To minimize semiconductor circuit power consumption, most Integrated Circuits (ICs) are made in the well-known complementary insulated gate FET technology known as CMOS. Moreover, state of the art CMOS chips are frequently made in a silicon on insulator (SOI) technology, where CMOS devices are formed in a thin uniform silicon surface layer. Whether on a bulk wafer or in SOI, typical CMOS circuit includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal.
In an ideal NFET, for example, current only flows when the gate to source voltage (Vgs) exceeds the device threshold voltage (VT) and is determined in part by the amount which it exceeds VT, i.e., by Vgs−VT. PFETs operate analogously. FET drain to source current (Ids, which is considered DC current and so, DC power (IdsVsupply) consumed) is dependent upon circuit conditions, device characteristics (e.g., width, length, channel mobility and threshold voltage) and device voltages.
Since the pair of devices in an ideal inverter have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is on and conducting (modeled simply as a closed switch), the other device (the PFET) is off, not conducting (ideally modeled as an open switch) and, vice versa. Thus, ideally, there is no static or DC current path in a typical CMOS circuit and ideal CMOS circuits use no static or DC power and only consume transient power from charging and discharging capacitive loads.
In practice, however, typical FETs are much more complex than switches. So, transient power for circuit loads (from switching currents) accounts for only a portion of CMOS chip power. Especially since device VT is directly proportional to gate dielectric thickness and also dependent on channel length, as FET features (including gate dielectric and channel length and thickness) shrink, current may continue to flow through off FETs causing what is known as subthreshold current. Subthreshold current is current conduction at gate biases below FET threshold and is directly proportional to gate width. Also, gate oxide leakage also became a major source static power loss. By replacing gate oxide with high-k dielectrics most of this gate oxide leakage has been eliminated.
However, polysilicon cannot be used with high-k dielectrics. Also, parasitic circuit resistances reduce performance and complicate design. A source of parasitic circuit resistances has been in the polysilicon used to form FET gates. Consequently, polysilicon is being replaced with wok function metal and aluminum in what is known as Replacement Metal Gate (RMG) FET technologies.
Further, reducing RMGFET lengths has degraded device transconductances (Gm/Gds) in addition to increasing subthreshold current. For a particular device, subthreshold current increases exponentially with the magnitude of the device's drain to source voltage (Vds) and reduces exponentially with the magnitude of the device's VT.
Subthreshold current is especially troublesome in achieving what is known as low VT devices, where the VT may be less than 100 millivolts (100 mV). Since these and other effects become more pronounced as the devices become shorter, they are commonly known collectively as short channel effects (SCEs). Metal gates in RMGFETS, even with high work function metals, have a lower work function than polysilicon. RMGFETs require lower channel doping levels or counter doping for low VT devices than equivalent polysilicon gate devices. So, low VT RMGFETs are much more susceptible to short channel effects than equivalent polysilicon gate devices and RMGPFETs are worse than RMGNFETs.
Consequently, especially for complex chips and arrays with a large number of devices, short channel effects can be overwhelming. When multiplied by the millions and even billions of devices on a state of the art IC, even 100 picoAmps (100 pA) of leakage in each of a million circuits, for example, results in chip leakage on the order of 100 milliAmps (100 mA).
Further, these short channel effects are much worse at operating conditions beyond nominal, e.g., higher supply voltages. However, frequently ICs require some devices to operate at higher voltages, e.g., in analog applications and in Input/Output (I/O) building blocks. For these applications devices with process normal (low VT) but thicker than nominal gate dielectric are essential. Typically, to achieve low VTs channel doping is selectively reduced or channels are selectively counter doped, either of which degrades device performance.
Thus, there exists a need in Integrated Circuits (ICs) for higher performance PFETs with reduced short channel effects; and more particularly, to reduce PFET VTs and channel lengths in ICs without reduced/counter doping channels even while minimizing PFET short channel effects.